Written and maintained by CASRAI Editorial Board
Last updated
Short answer: Wafer-level packaging (WLP) is a family of integrated-circuit packaging methods in which the package is built while the dies are still part of the wafer, rather than after each die is cut out and mounted individually. In the simplest form, a wafer-level chip-scale package (WLCSP), the package is finished when the wafer is singulated. Fan-out variants add redistribution layers that extend beyond the die edge.
What wafer-level packaging is
A review in Frontiers in Electronics (2024) describes WLP as packaging integrated circuits and other components while they are still on the wafer, and notes that processing whole wafers lowers manufacturing cost and improves yield. Texas Instruments’ application note AN-1112 (rev. December 2019) puts the same idea for its DSBGA product: the package is “completely processed in wafer form; and when singulated, the package is complete.” The package outline matches the die outline, there is no interposer between the IC and the printed circuit board (PCB), and the footprint per I/O is the smallest of the package types TI describes.
For a lab or prototyping group this matters mostly at the bench: a die-sized package has no leads and no substrate, so board design and assembly settings are less forgiving than for a conventional leaded package.
Fan-in versus fan-out
| Feature | Fan-in WLP | Fan-out WLP |
|---|---|---|
| Redistribution layers (RDLs) | Stay within the die footprint | Extend beyond the size of the die, together with the solder balls |
| I/O capacity | Modest; described as an option for low-end mobile devices | More I/O while keeping a thin profile |
| Construction | Processed on the original wafer, then singulated | Dies are placed on a carrier wafer, molded, then singulated, with RDLs built on the exposed dies |
Source: Frontiers in Electronics 2024 warpage review, read 2026-11-08. The same review links application areas to variants: core fan-out mainly to automotive and network uses, high-density fan-out mostly to mobile and antenna-in-package, and ultra-high-density fan-out to network and server uses, with demand driven by autonomous driving, AI, consumer electronics, networking infrastructure, high-performance computing and IoT.
Terminology differences
Sources do not use the terms identically. The Frontiers review treats WLCSP as the fan-in type, while vendors use “WLCSP”, “wafer-level chip-scale package” and “DSBGA” (TI’s name) for die-sized packages, and Amkor’s WLP page groups chip-scale, fan-out, 3D and system-in-package schemes under one heading. When you compare datasheets, check which structure is actually meant before comparing specifications.
How a WLCSP is made
TI’s note lists the sequence for its DSBGA parts: standard wafer fabrication, re-passivation, solder bumps on the I/O pads, backgrinding, a protective encapsulation coating, wafer-sort test, laser marking, singulation, and tape and reel. The parts are then assembled with standard surface-mount technology (SMT).
Assembling a WLCSP on a board: TI’s published guidance
The following checklist restates what TI AN-1112 says for its own DSBGA devices. It is manufacturer guidance for those parts, not an industry-wide rule, so follow the datasheet of the part you actually use.
| Item | What AN-1112 states |
|---|---|
| Pad definition | Non-solder-mask-defined (NSMD) pads preferred over solder-mask-defined |
| Copper and traces | Copper under 1 oz; trace width no more than two-thirds of the pad diameter |
| Surface finish | OSP or ENIG (gold under 0.2 micron); HASL not recommended |
| Paste and stencil | Type 3 paste or finer; laser-cut, electropolished stencils |
| Reflow | Qualified for up to three reflows at 260 °C peak per J-STD-020 |
| Placement force | About 1 kg for 0.5 s maximum |
| Moisture sensitivity | All DSBGA parts are MSL level 1 (unlimited floor life at 30 °C or below and 60% RH) |
| Underfill | Designed for board-level thermal-cycling reliability without underfill in the intended applications; if used, fillet partway up the die edges, CTE close to solder, Tg above the maximum exposure temperature |
TI also lists standard bump arrays from 2×2 to 11×11, package heights of 0.35 to 0.55 mm, pitches of 0.3, 0.35, 0.4 and 0.5 mm, and a maximum thickness of 0.3 mm for its PowerWCSP variant. Write these numbers into your assembly procedure only after checking them against the part’s current datasheet; see how to write a lab SOP and the SOP dictionary entry for structuring that document, and facility qualification for qualifying the equipment, such as a reflow oven, that the process depends on.
Warpage in fan-out packaging
The Frontiers review defines warpage as an out-of-plane deformation that disrupts handling, alignment and RDL patterning. It names these causes: thermal-expansion mismatch in the die, mold and carrier stack; changes in molding-compound properties; stress released at debonding; thermal stress during reflow; mechanical stress from backgrinding; and the stiffness and expansion mismatch between copper traces and polyimide in the RDL. Because several causes act together, warpage is managed as a process-wide problem rather than fixed at one step.
Common misunderstandings
- “Wafer-level” does not mean every step happens on the wafer. Singulation, and for fan-out the reconstitution onto a carrier wafer, change the picture; the sources describe both.
- Wafer-level does not automatically mean fan-in. Fan-out WLP is also wafer-level, with RDLs reaching beyond the die edge.
- Assembly numbers are not universal. The pad, finish and reflow limits above are TI’s for DSBGA parts.
- Calibration of the tools still applies. Placement and reflow settings are only meaningful if the equipment is controlled; see what is calibration.
FAQ
What is the difference between WLP and WLCSP?
WLP is the broad category; WLCSP is the die-sized, fan-in form in which the package is complete when the wafer is cut, as TI and the Frontiers review describe it.
Does a WLCSP need underfill?
TI says its DSBGA parts are designed for board-level thermal-cycling reliability without underfill in the intended applications, and gives selection criteria if underfill is used. Other vendors’ parts may differ.
Why does fan-out WLP warp?
Mainly thermal-expansion mismatch across the die, mold compound and carrier, plus stresses from debonding, reflow and backgrinding, per the Frontiers review.
Sources
- “Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies,” Frontiers in Electronics, 2024, doi 10.3389/felec.2024.1515860 (read 2026-11-08).
- Texas Instruments, AN-1112 “DSBGA Wafer Level Chip Scale Package,” SNVA009AI, revised December 2019 (read 2026-11-08).
- Amkor Technology, wafer-level packaging overview page (read 2026-11-08).
