On November 13, 2026, Marvell Technology announced a comprehensive AI and high-performance computing interconnect showcase for the Supercomputing 2026 (SC26) conference in Chicago, introducing optical Photonic Fabric memory modules and second-generation Structera X CXL 3.2 expanders designed to eliminate memory capacity and bandwidth bottlenecks across multi-rack scientific computing clusters.
Marvell SC26 Showcase: Architecture for the Post-Memory-Wall Era
Ahead of the Supercomputing 2026 (SC26) conference running November 15–20, 2026, at McCormick Place in Chicago, Marvell Technology, Inc. unveiled an extensive portfolio of memory expansion, optical interconnect, and high-density switching silicon. According to Marvell’s official announcement released through its investor newsroom, the showcase at booth #4003 targets the primary performance bottleneck in large-scale AI and high-performance computing (HPC): the disparity between accelerator compute capacity and interconnect memory bandwidth.
As artificial intelligence workloads transition toward long-context reasoning and agentic workflows, dynamic memory demands routinely exceed single-server limits. In supercomputing environments, compute nodes executing intensive numerical simulations often leave accelerators idle while waiting for memory transfers over congested fabrics. Marvell’s SC26 demonstrations address scale-up, scale-out, and scale-across domains to unite memory tiers into a coherent system fabric.
Photonic Fabric and CXL 3.2: Technical Specifications and Architecture
The centerpiece of Marvell’s showcase is the Marvell Photonic Fabric memory module, an optical disaggregated memory architecture designed to bypass copper reach limits. Replacing power-hungry electronic switches with direct optical I/O and a passive fiber shuffle, this switchless full-crossbar topology connects up to 16 host nodes to a shared memory pool of up to 32 terabytes (TB) with sub-350 nanosecond near-NUMA latency.
In parallel, Marvell demonstrated its Compute Express Link (CXL) portfolio, featuring second-generation Structera X expansion controllers. Built for CXL 3.2 over PCIe Gen 6 links, Structera X 3406 and 3506 controllers provide six channels supporting DDR4 and DDR5, unlocking up to 9 TB of direct memory expansion per module alongside hardware compression and near-memory compute acceleration.
The following table outlines Marvell’s interconnect technologies relative to conventional cluster memory architectures:
| Interconnect Tier | Physical Medium | Maximum Pool Capacity | Target Latency | Primary Application |
|---|---|---|---|---|
| Direct Host HBM / DDR5 | On-package / PCB copper traces | 96 GB to 2 TB per node | Under 100 ns | Primary compute kernel execution |
| Electrical CXL 2.0 / 3.0 | PCIe copper / Retimers | 2 TB to 4 TB per chassis | 250–400 ns | Chassis-level memory pooling |
| Marvell Structera X (CXL 3.2) | PCIe Gen 6 / AEC copper | Up to 9 TB per controller | 180–300 ns | Multi-channel memory expansion and compression |
| Marvell Photonic Fabric Module | Passive optical fiber shuffle | Up to 32 TB across 16 hosts | Sub-350 ns near-NUMA | Multi-rack KV cache and shared HPC pools |
Marvell also demonstrated 102.4 Tbps Teralynx T100 switch silicon in a data center simulator, Multipath Reliable Connection (MRC) protocols on Teralynx 10 switches, Alaska A Active Electrical Cables (AECs) supporting 800 Gbps and 1.6 Tbps transmission, and Bravera SSD controllers with OCTEON data processing units (DPUs) for disaggregated storage.
The Memory Wall: From Single-Rack Limits to Optical Disaggregation
In transformer inference, Key-Value (KV) caching for large language models requires tens of terabytes of capacity at hundreds of gigabytes per second. While host-memory KV caching delivers up to a 100x speedup over re-computation, single-node systems support only dozens of concurrent long-context sessions before encountering memory exhaustion.
When local accelerator memory fills, clusters hit an eviction cliff, forcing cache drops or spillover to high-latency storage. As detailed in research on arXiv (arXiv:2607.27187), Marvell’s photonic-CXL hybrid architecture cuts latency by over 50 percent versus electrical CXL switch pools, eliminating eviction cliffs and boosting Time-To-First-Token (TTFT) by 6.6x for multi-turn conversational agents.
High-performance computing faces an identical barrier. Leadership supercomputers like the El Capitan supercomputer require massive working sets for nuclear physics and climate modeling. When research campaigns through the ASCR Leadership Computing Challenge (ALCC) scale across thousands of nodes, message passing overhead and memory fragmentation constrain efficiency. Optical memory pooling decouples memory provisioning from rigid CPU-GPU socket ratios.
Industry Reaction and Expert Perspectives at SC26
Infrastructure specialists at SC26 noted that disaggregated pooling marks a major turning point in cluster design. Preet Virk, Senior Vice President and General Manager of the Photonic Fabric Business Unit at Marvell, explained that optical interconnects allow memory and compute to scale together across multiple racks, expanding the scale-up domain beyond the thermal and physical limits of a single server chassis.
These technologies feature prominently in the SC26 Birds of a Feather session titled Photonics for AI & HPC Clusters: Breaking the Bandwidth and Power Barrier, scheduled for November 18, 2026, in Room W184bcd at McCormick Place, per the SC26 official conference program. Panelists including Dan Olds, Phil Pokorny, Andy Mills, Luis Ancajas, and Preet Virk will examine how optical switch fabrics and co-packaged optics curb power consumption while delivering multi-terabyte bandwidth.
Independent infrastructure reporting from Data Center Frontier and market coverage by Morningstar corroborate that academic and cloud facilities are accelerating CXL deployments to eliminate stranded compute and optimize infrastructure capital costs.
Implications for University HPC Centers and Scientific Research
For university research computing leaders, the introduction of commercial optical fabrics and CXL 3.2 controllers offers practical institutional benefits:
- Capital Efficiency: Rather than over-provisioning memory across all compute nodes, CXL 3.2 expansion allows dynamic allocation of pooled memory to jobs that require large context, maximizing utilization of costly GPU assets.
- AI Scientific Benchmarks: Optical memory pools sustain large context windows for drug discovery and material synthesis, supporting deterministic execution for reproducible AI experiments without unpredictable cache evictions.
- Scheduler Integration: Workload schedulers like Slurm can treat CXL-attached memory as a schedulable resource, creating a composable computational environment tailored to multi-tenant campus workloads.
- Facility Power Reductions: Passive optical shuffles reduce switching power compared to active electronic fabrics, lowering heat loads on university datacenter cooling infrastructure.
Deployment Timelines and Next Steps in Cluster Interconnects
Following SC26 demonstrations at booth #4003, Marvell plans to sample Structera X CXL 3.2 memory expanders in early 2027, with volume manufacturing ramping alongside PCIe Gen 6 server architectures. ODM reference platforms featuring Teralynx T100 switch trays and Photonic Fabric modules are slated for partner testing across 2027.
Marvell is also aligning its roadmap with open standards through the CXL Consortium, the Ultra Accelerator Link (UALink) group, and the Ultra Ethernet Consortium (UEC), ensuring multi-vendor interoperability for future academic and national lab upgrades.
Sources
- Marvell Scales Connectivity to Address AI Infrastructure’s Next Bottleneck at Supercomputing 2026 — Marvell Technology, Inc. Investor Relations (2026-11-13)
- Marvell Scales Connectivity to Address AI Infrastructure’s Next Bottleneck at Supercomputing 2026 — Morningstar / Business Wire (2026-11-13)
- A Photonic-CXL Memory Appliance for Scalable KV Cache Management in LLM Inference — arXiv:2607.27187 [cs.AR] (2026-07-28)
- Photonics for AI & HPC Clusters: Breaking the Bandwidth and Power Barrier (SC26 Birds of a Feather Session) — Supercomputing 2026 Conference Program (2026-11-15)
- Penguin Solutions Introduces Industry’s First Production-Ready CXL-Based KV Cache Server — Data Center Frontier (2026-08-14)
